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SH7101 Datasheet(PDF) 256 Page - Renesas Technology Corp

Part # SH7101
Description  32-Bit RISC Microcomputer
PDF  560 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7101 Datasheet(HTML) 256 Page - Renesas Technology Corp

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Section 8 Multifunction Timer Pulse Unit (MTU)
Rev.1.00 Sep. 18, 2008 Page 222 of 522
REJ09B0069-0100
8.7.7
Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR
by the buffer operation differs depending on channel 0 and channels 3 and 4: data on channel 0 is
that after write, and on channels 3 and 4, before write.
Figures 8.73 and 8.74 show the timing in this case.
Compare
match buffer
signal
Compare
match signal
Write signal
Address
P
φ
Buffer register
address
Buffer register
TGR write cycle
T1
T2
M
TGR
N
M
Buffer register write data
Figure 8.73 Contention between Buffer Register Write and Compare Match (Channel 0)



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