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SH7101 Datasheet(PDF) 253 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 253 Page - Renesas Technology Corp |
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253 / 560 page ![]() Section 8 Multifunction Timer Pulse Unit (MTU) Rev.1.00 Sep. 18, 2008 Page 219 of 522 REJ09B0069-0100 Overlap Phase differ- ence Phase differ- ence Overlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Pulse width Pulse width Notes: Phase difference and overlap Pulse width : 1.5 states or more : 2.5 states or more Figure 8.69 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode 8.7.3 Caution on Period Setting When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f = P φ (N + 1) Where f : Counter frequency P φ : Peripheral clock operating frequency N : TGR set value 8.7.4 Contention between TCNT Write and Clear Operations If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 8.70 shows the timing in this case. |
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