SH7101 datasheet(312/560 Pages) RENESAS

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Section 9 Watchdog Timer

Rev.1.00 Sep. 18, 2008 Page 278 of 522

REJ09B0069-0100

9.4.3

Clearing Software Standby Mode

The watchdog timer has a special function to clear software standby mode with an NMI interrupt

IRQ0 to IRQ3 interrupts. When using software standby mode, set the WDT as described below.

Before Transition to Software Standby Mode: The TME bit in TCSR must be cleared to 0 to

stop the watchdog timer counter before entering software standby mode. The chip cannot enter

software standby mode while the TME bit is set to 1. Set bits CKS2 to CKS0 in TCSR so that the

counter overflow interval is equal to or longer than the oscillation settling time. See section 20.3,

AC Characteristics, for the oscillation settling time.

Recovery from Software Standby Mode: When an NMI signal or

IRQ0 to IRQ3 signals are

received in software standby mode, the clock oscillator starts running and TCNT starts

incrementing at the rate selected by bits CKS2 to CKS0 before software standby mode was

entered. When TCNT overflows (changes from H'FF to H'00), the clock is presumed to be stable

and usable; clock signals are supplied to the entire chip and software standby mode ends.

For details on software standby mode, see section 18, Power-Down Modes.

9.4.4

Timing of Setting the Overflow Flag (OVF)

In interval timer mode, when TCNT overflows, the OVF bit of TCSR is set to 1 and an interval

timer interrupt (ITI) is simultaneously requested. Figure 9.4 shows this timing.

TCNT

Overflow signal

(internal signal)

OVF

H'FF

H'00

Figure 9.4 Timing of Setting OVF

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