SH7101 datasheet(309/560 Pages) RENESAS

309 / 560 page

Section 9 Watchdog Timer

Rev.1.00 Sep. 18, 2008 Page 275 of 522

REJ09B0069-0100

9.3.3

Reset Control/Status Register (RSTCSR)

RSTCSR is an 8-bit readable/writable register that controls the generation of the internal reset

signal when TCNT overflows, and selects the type of internal reset signal.

Bit

Bit Name

Initial

Value

R/W

Description

WOVF

R/(W)*

Watchdog Overflow Flag

This bit is set when TCNT overflows in watchdog timer

mode. This bit cannot be set in interval timer mode.

[Setting condition]

• Set when TCNT overflows in watchdog timer mode

[Clearing condition]

• Cleared by reading WOVF, and then writing 0 to

WOVF

RSTE

R/W

Reset Enable

Specifies whether or not a reset signal is generated in

the chip if TCNT overflows in watchdog timer mode.

0: Reset signal is not generated even if TCNT overflows

(Though this LSI is not reset, TCNT and TCSR in

WDT are reset)

1: Reset signal is generated if TCNT overflows

RSTS

R/W

Reset Select

Selects the type of internal reset generated if TCNT

overflows in watchdog timer mode.

0: Power-on reset

1: Manual reset

4 to 0

—

All 1

Reserved

These bits are always read as 1. The write value should

always be 1.

Note:

Only 0 can be written, for flag clearing.

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