SH7101 datasheet(307/560 Pages) RENESAS

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Section 9 Watchdog Timer

Rev.1.00 Sep. 18, 2008 Page 273 of 522

REJ09B0069-0100

• Timer control/status register (TCSR)

• Timer counter (TCNT)

• Reset control/status register (RSTCSR)

9.3.1

Timer Counter (TCNT)

TCNT is an 8-bit readable/writable upcounter. When the timer enable bit (TME) in the timer

control/status register (TCSR) is set to 1, TCNT starts counting pulses of an internal clock selected

by clock select bits 2 to 0 (CKS2 to CKS0) in TCSR. When the value of TCNT overflows

(changes from H'FF to H'00), a watchdog timer overflow signal (

WDTOVF) or interval timer

interrupt (ITI) is generated, depending on the mode selected in the WT/

IT bit of TCSR. The initial

value of TCNT is H'00.

9.3.2

Timer Control/Status Register (TCSR)

TCSR is an 8-bit readable/writable register. Its functions include selecting the clock source to be

input to TCNT, and the timer mode.

Bit

Bit Name

Initial Value

R/W

Description

OVF

R/(W)*

Overflow Flag

Indicates that TCNT has overflowed in interval timer

mode. This bit should only be written with 0 to clear

the flag. This flag is not set in watchdog timer mode.

[Setting condition]

• When TCNT overflows in interval timer mode

[Clearing conditions]

• Cleared by reading OVF

• When 0 is written to the TME bit in interval timer

mode

WT/

R/W

Timer Mode Select

Selects whether the WDT is used as a watchdog

timer or interval timer. When TCNT overflows, the

WDT either generates an interval timer interrupt (ITI)

or generates a

WDTOVF signal, depending on the

mode selected.

0: Interval timer mode

Interval timer interrupt (ITI) request to the CPU

when TCNT overflows

1: Watchdog timer mode

WDTOVF signal output externally when TCNT

overflows*

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