SH7101 datasheet(308/560 Pages) RENESAS

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Section 9 Watchdog Timer

Rev.1.00 Sep. 18, 2008 Page 274 of 522

REJ09B0069-0100

Bit

Bit Name

Initial Value

R/W

Description

TME

R/W

Timer Enable

Enables or disables the timer.

0: Timer disabled

TCNT is initialized to H'00 and count-up stops

1: Timer enabled

TCNT starts counting. A

WDTOVF signal or

interrupt is generated when TCNT overflows.

4, 3

—

All 1

Reserved

These bits are always read as 1. The write value

should always be 1.

CKS2

CKS1

CKS0

R/W

Clock Select 2 to 0

Select one of eight internal clock sources for input to

TCNT. The clock signals are obtained by dividing the

frequency of the system clock (

φ). The overflow

frequency for

φ = 40 MHz is enclosed in

parentheses*

000: Clock

φ/2 (period: 12.8 μs)

001: Clock

φ/64 (period: 409.6 μs)

010: Clock

φ/128 (period: 0.8 ms)

011: Clock

φ/256 (period: 1.6 ms)

100: Clock

φ/512 (period: 3.3 ms)

101: Clock

φ/1024 (period: 6.6 ms)

110: Clock

φ/4096 (period: 26.2 ms)

111: Clock

φ/8192 (period: 52.4 ms)

Notes: 1. Only 0 can be written after reading 1.

2. Section 9.3.3, Reset Control/Status Register (RSTCSR), describes in detail what

happens when TCNT overflows in watchdog timer mode.

3. The overflow interval listed is the time from when the TCNT begins counting at H'00

until an overflow occurs.

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