HD6433644R datasheet(331/549 Pages) RENESAS

331 / 549 page

Section 10 Serial Communication Interface

Rev. 6.00 Sep 12, 2006 page 311 of 526

REJ09B0326-0600

Table 10.12 SMR and SCR3 Settings and Clock Source Selection

SMR

SCR3

Transmit/Receive Clock

Bit 7:

COM

Bit 1:

CKE1

Bit 0:

CKE0

Mode

Clock

Source

SCK3 Pin Function

Asynchronous

Internal

I/O port (SCK3 pin not used)

mode

Outputs clock with same frequency as

bit rate

External

Inputs clock with frequency 16 times

bit rate

Synchronous

Internal

Outputs serial clock

mode

External

Inputs serial clock

Reserved (Do not specify these combinations)

Interrupts and Continuous Transmission/Reception: SCI3 can carry out continuous reception

using RXI and continuous transmission using TXI. These interrupts are shown in table 10.13.

Table 10.13 Transmit/Receive Interrupts

Interrupt Flags

Interrupt Request Conditions

Notes

RXI

RDRF

RIE

When serial reception is performed

normally and receive data is transferred

from RSR to RDR, bit RDRF is set to 1,

and if bit RIE is set to 1 at this time, RXI

is enabled and an interrupt is requested.

(See figure 10.7 (a).)

The RXI interrupt routine reads the

receive data transferred to RDR

and clears bit RDRF to 0.

Continuous reception can be

performed by repeating the above

operations until reception of the

next RSR data is completed.

TXI

TDRE

TIE

When TSR is found to be empty (on

completion of the previous transmission)

and the transmit data placed in TDR is

transferred to TSR, bit TDRE is set to 1. If

bit TIE is set to 1 at this time, TXI is

enabled and an interrupt is requested.

(See figure 10.7 (b).)

The TXI interrupt routine writes the

next transmit data to TDR and

clears bit TDRE to 0. Continuous

transmission can be performed by

repeating the above operations until

the data transferred to TSR has

been transmitted.

TEI

TEND

TEIE

When the last bit of the character in TSR

is transmitted, if bit TDRE is set to 1, bit

TEND is set to 1. If bit TEIE is set to 1 at

this time, TEI is enabled and an interrupt

is requested. (See figure 10.7 (c).)

TEI indicates that the next transmit

data has not been written to TDR

when the last bit of the transmit

character in TSR is sent.

HD6433644R Datasheet(PDF) 331 Page - Renesas Technology Corp

HD6433644R Datasheet(HTML) 331 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL