HD6433644R datasheet(369/549 Pages) RENESAS

369 / 549 page

Section 12 A/D Converter

Rev. 6.00 Sep 12, 2006 page 349 of 526

REJ09B0326-0600

Bit 7



Clock Select (CKS): Bit 7 sets the A/D conversion speed.

Conversion Time

Bit 7: CKS

Conversion Period

φφφφ = 2 MHz

φφφφ = 5 MHz

φφφφ = 8 MHz*

62/

φ (initial value)

31 µs

12.4 µs

7.75 µs

31/

15.5 µs

*



Notes: 1. Applies only to F-ZTAT, R of the ZTAT, and R of the mask ROM version.

2. Operation is not guaranteed if the conversion time is less than 12.4 µs. Set bit 7 for a

value of at least 12.4 µs.

Bit 6



External Trigger Select (TRGE): Bit 6 enables or disables the start of A/D conversion by

external trigger input.

Bit 6: TRGE

Description

Disables start of A/D conversion by external trigger

(initial value)

Enables start of A/D conversion by rising or falling edge of external trigger at

ADTRG*

Note:

* The external trigger (

ADTRG) edge is selected by bit INTEG5 of IEGR2. See section

3.3.2, Interrupt Edge Select Register 2 (IEGR2) for details.

Bits 5 and 4



Reserved Bits: Bits 5 and 4 are reserved; they are always read as 1, and cannot be

modified.

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