HD6433644R datasheet(227/549 Pages) RENESAS

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Section 9 Timers

Rev. 6.00 Sep 12, 2006 page 207 of 526

REJ09B0326-0600

Bit 4



Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified.

Bits 3 to 0



Internal Clock Select (TMA3 to TMA0): Bits 3 to 0 select the clock input to TCA.

The selection is made as follows.

Description

Bit 3:

TMA3

Bit 2:

TMA2

Bit 1:

TMA1

Bit 0:

TMA0

Prescaler and Divider Ratio

or Overflow Period

Function

PSS,

φ/8192

(initial value)

Interval timer

PSS,

φ/4096

PSS,

φ/2048

PSS,

φ/512

PSS,

φ/256

PSS,

φ/128

PSS,

φ/32

PSS,

φ/8

PSW, 1 s

Clock time base

PSW, 0.5 s

PSW, 0.25 s

PSW, 0.03125 s

PSW and TCA are reset

Timer Counter A (TCA)

Bit

TCA7

TCA6

TCA5

TCA4

TCA3

TCA2

TCA1

TCA0

Initial value

Read/Write

TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock

source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A

(TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive

mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1.

HD6433644R Datasheet(PDF) 227 Page - Renesas Technology Corp

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