HD6433644R datasheet(228/549 Pages) RENESAS

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Section 9 Timers

Rev. 6.00 Sep 12, 2006 page 208 of 526

REJ09B0326-0600

TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11.

Upon reset, TCA is initialized to H'00.

9.2.3

Timer Operation

Interval Timer Operation: When bit TMA3 in timer mode register A (TMA) is cleared to 0,

timer A functions as an 8-bit interval timer.

Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval

timing resume immediately. The clock input to timer A is selected by bits TMA2 to TMA0 in

TMA; any of eight internal clock signals output by prescaler S can be selected.

After the count value in TCA reaches H'FF, the next clock signal input causes timer A to

overflow, setting bit IRRTA to 1 in interrupt request register 1 (IRR1). If IENTA = 1 in interrupt

enable register 1 (IENR1), a CPU interrupt is requested.*

At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A functions as

an interval timer that generates an overflow output at intervals of 256 input clock pulses.

Note: * For details on interrupts, see section 3.3, Interrupts.

Real-Time Clock Time Base Operation: When bit TMA3 in TMA is set to 1, timer A functions

as a real-time clock time base by counting clock signals output by prescaler W. The overflow

period of timer A is set by bits TMA1 and TMA0 in TMA. A choice of four periods is available.

In time base operation (TMA3 = 1), setting bit TMA2 to 1 clears both TCA and prescaler W to

their initial values of H'00.

Clock Output: Setting bit TMOW in port mode register 1 (PMR1) to 1 causes a clock signal to be

output at pin TMOW. Eight different clock output signals can be selected by means of bits TMA7

to TMA5 in TMA. The system clock divided by 32, 16, 8, or 4 can be output in active mode and

sleep mode. A 32.768 kHz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep

mode, and subactive mode.

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