HD6433644R datasheet(232/549 Pages) RENESAS

232 / 549 page

Section 9 Timers

Rev. 6.00 Sep 12, 2006 page 212 of 526

REJ09B0326-0600

Bits 2 to 0



Clock Select (TMB12 to TMB10): Bits 2 to 0 select the clock input to TCB1. For

external event counting, either the rising or falling edge can be selected.

Bit 2: TMB12

Bit 1: TMB11

Bit 0: TMB10

Description

Internal clock:

φ/8192

(initial value)

Internal clock:

φ/2048

Internal clock:

φ/512

Internal clock:

φ/256

Internal clock:

φ/64

Internal clock:

φ/16

Internal clock:

φ/4

External event (TMIB): rising or falling edge*

Note:

* The edge of the external event signal is selected by bit INTEG6 in interrupt edge select

Timer Counter B1 (TCB1)

Bit

TCB17

TCB16

TCB15

TCB14

TCB13

TCB12

TCB11

TCB10

Initial value

Read/Write

TCB1 is an 8-bit read-only up-counter, which is incremented by internal clock or external event

input. The clock source for input to this counter is selected by bits TMB12 to TMB10 in timer

mode register B1 (TMB1). TCB1 values can be read by the CPU at any time.

When TCB1 overflows from H'FF to H'00 or to the value set in TLB1, the IRRTB1 bit in IRR1 is

set to 1.

TCB1 is allocated to the same address as TLB1.

Upon reset, TCB1 is initialized to H'00.

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