HD6433644R datasheet(233/549 Pages) RENESAS

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Section 9 Timers

Rev. 6.00 Sep 12, 2006 page 213 of 526

REJ09B0326-0600

Timer Load Register B1 (TLB1)

Bit

TLB17

TLB16

TLB15

TLB14

TLB13

TLB12

TLB11

TLB10

Initial value

Read/Write

TLB1 is an 8-bit write-only register for setting the reload value of timer counter B1 (TCB1).

When a reload value is set in TLB1, the same value is loaded into timer counter B1 (TCB1) as

well, and TCB1 starts counting up from that value. When TCB1 overflows during operation in

auto-reload mode, the TLB1 value is loaded into TCB1. Accordingly, overflow periods can be set

within the range of 1 to 256 input clocks.

The same address is allocated to TLB1 as to TCB1.

Upon reset, TLB1 is initialized to H'00.

9.3.3

Timer Operation

Interval Timer Operation: When bit TMB17 in timer mode register B1 (TMB1) is cleared to 0,

timer B1 functions as an 8-bit interval timer.

Upon reset, TCB1 is cleared to H'00 and bit TMB17 is cleared to 0, so up-counting and interval

timing resume immediately. The clock input to timer B1 is selected from seven internal clock

signals output by prescaler S, or an external clock input at pin TMIB. The selection is made by bits

TMB12 to TMB10 of TMB1.

After the count value in TCB1 reaches H'FF, the next clock signal input causes timer B1 to

overflow, setting bit IRRTB1 to 1 in interrupt request register 1 (IRR1). If IENTB1 = 1 in

interrupt enable register 1 (IENR1), a CPU interrupt is requested.*

At overflow, TCB1 returns to H'00 and starts counting up again.

During interval timer operation (TMB17 = 0), when a value is set in timer load register B1

(TLB1), the same value is set in TCB1.

Note: * For details on interrupts, see section 3.3, Interrupts.

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