HD6433644R datasheet(235/549 Pages) RENESAS

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Section 9 Timers

Rev. 6.00 Sep 12, 2006 page 215 of 526

REJ09B0326-0600

9.4

Timer V

9.4.1

Overview

Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Also compare

match signals can be used to reset the counter, request an interrupt, or output a pulse signal with an

arbitrary duty cycle. Counting can be initiated by a trigger input at the TRGV pin, enabling pulse

output control to be synchronized to the trigger, with an arbitrary delay from the trigger input.

Features

Features of timer V are given below.

• Choice of six internal clock sources (φ/128, φ/64, φ/32, φ/16, φ/8, φ/4) or an external clock (can

be used as an external event counter).

• Counter can be cleared by compare match A or B, or by an external reset signal. If the count

stop function is selected, the counter can be halted when cleared.

• Timer output is controlled by two independent compare match signals, enabling pulse output

with an arbitrary duty cycle, PWM output, and other applications.

• Three interrupt sources: two compare match, one overflow

• Counting can be initiated by trigger input at the TRGV pin. The rising edge, falling edge, or

both edges of the TRGV input can be selected.

HD6433644R Datasheet(PDF) 235 Page - Renesas Technology Corp