HD6433644R datasheet(238/549 Pages) RENESAS

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Section 9 Timers

Rev. 6.00 Sep 12, 2006 page 218 of 526

REJ09B0326-0600

9.4.2

Timer Counter V (TCNTV)

Bit

TCNTV7 TCNTV6 TCNTV5 TCNTV4 TCNTV3 TCNTV2 TCNTV1 TCNTV0

Initial value

Read/Write

R/W

TCNTV is an 8-bit read/write up-counter which is incremented by internal or external clock input.

The clock source is selected by bits CKS2 to CKS0 in TCRV0. The TCNTV value can be read and

written by the CPU at any time. TCNTV can be cleared by an external reset signal, or by compare

match A or B. The clearing signal is selected by bits CCLR1 and CCLR0 in TCRV0.

When TCNTV overflows from H'FF to H'00, OVF is set to 1 in TCSRV.

TCNTV is initialized to H'00 upon reset and in standby mode, watch mode, subsleep mode, and

subactive mode.

Time Constant Registers A and B (TCORA, TCORB)

Bit

TCORn7 TCORn6 TCORn5 TCORn4 TCORn3 TCORn2 TCORn1 TCORn0

Initial value

Read/Write

R/W

n = A or B

TCORA and TCORB are 8-bit read/write registers.

TCORA and TCNTV are compared at all times, except during the T3 state of a TCORA write

cycle. When the TCORA and TCNTV contents match, CMFA is set to 1 in TCSRV. If CMIEA is

also set to 1 in TCRV0, a CPU interrupt is requested.

Timer output from the TMOV pin can be controlled by a signal resulting from compare match,

according to the settings of bits OS3 to OS0 in TCSRV.

TCORA is initialized to H'FF upon reset and in standby mode, watch mode, subsleep mode, and

subactive mode.

TCORB is similar to TCORA.

HD6433644R Datasheet(PDF) 238 Page - Renesas Technology Corp