HD6433644R datasheet(240/549 Pages) RENESAS

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Section 9 Timers

Rev. 6.00 Sep 12, 2006 page 220 of 526

REJ09B0326-0600

If TRGE is cleared to 0, after TCNTV is cleared it continues counting up.

Bit 4: CCLR1

Bit 3: CCLR0

Description

Clearing is disabled

(initial value)

Cleared by compare match A

Cleared by compare match B

Cleared by rising edge of external reset input

Bits 2 to 0



Clock Select 2 to 0 (CKS2 to CKS0): Bits 2 to 0 and bit ICKS0 in TCRV1 select

the clock input to TCNTV.

Six internal clock sources divided from the system clock (

φ) can be selected. The counter

increments on the falling edge.

If the external clock is selected, there is a further selection of incrementing on the rising edge,

falling edge, or both edges.

If TRGE is cleared to 0, after TCNTV is cleared it continues counting up.

TCRV0

TCRV1

Bit 2:

CKS2

Bit 1:

CKS1

Bit 0:

CKS0

Bit 0:

ICKS0

Description



Clock input disabled

(initial value)

Internal clock:

φ/4, falling edge

Internal clock:

φ/8, falling edge

Internal clock:

φ/16, falling edge

Internal clock:

φ/32, falling edge

Internal clock:

φ/64, falling edge

Internal clock:

φ/128, falling edge



Clock input disabled



External clock: rising edge



External clock: falling edge



External clock: rising and falling edges

HD6433644R Datasheet(PDF) 240 Page - Renesas Technology Corp

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