HD6433644R datasheet(244/549 Pages) RENESAS

244 / 549 page

Section 9 Timers

Rev. 6.00 Sep 12, 2006 page 224 of 526

REJ09B0326-0600

9.4.3

Timer Operation

Timer V Operation: A reset initializes TCNTV to H'00, TCORA and TCORB to H'FF, TCRV0

to H'00, TCSRV to H'10, and TCRV1 to H'E2.

Timer V can be clocked by one of six internal clocks output from prescaler S, or an external clock,

as selected by bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1. The valid edge or edges

of the external clock can also be selected by CKS2 to CKS0. When the clock source is selected,

TCNTV starts counting the selected clock input.

The TCNTV contents are always compared with TCORA and TCORB. When a match occurs, the

CMFA or CMFB bit is set to 1 in TCSRV. If CMIEA or CMIEB is set to 1 in TCRV0, a CPU

interrupt is requested. At the same time, the output level selected by bits OS3 to OS0 in TCSRV is

output from the TMOV pin.

When TCNT overflows from H'FF to H'00, if OVIE is 1 in TCRV0, a CPU interrupt is requested.

If bits CCLR1 and CCLR0 in TCRV0 are set to 01 (clear by compare match A) or 10 (clear by

compare match B), TCNTV is cleared by the corresponding compare match. If these bits are set to

11, TCNTV is cleared by input of a rising edge at the TMRIV pin.

When the counter clear event selected by bits CCLR1 and CCLR0 in TCRV0 occurs, TCNTV is

cleared and the count-up is halted. TCNTV starts counting when the signal edge selected by bits

TVEG1 and TVEG0 in TCRV1 is input at the TRGV pin.

HD6433644R Datasheet(PDF) 244 Page - Renesas Technology Corp