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HD6433644R Datasheet(PDF) 245 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 245 Page - Renesas Technology Corp |
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245 / 549 page  Section 9 Timers Rev. 6.00 Sep 12, 2006 page 225 of 526 REJ09B0326-0600 TCNTV Increment Timing: TCNTV is incremented by an input (internal or external) clock. • Internal clock One of six clocks ( φ/128, φ/64, φ/32, φ/16, φ/8, φ/4) divided from the system clock (φ) can be selected by bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1. Figure 9.4 shows the timing. N – 1 TCNTV input FRC input φ TCNTV Internal clock N N – 1 Figure 9.4 Increment Timing with Internal Clock • External clock Incrementation on the rising edge, falling edge, or both edges of the external clock can be selected by bits CKS2 to CKS0 in TCRV0. The external clock pulse width should be at least 1.5 system clocks ( φ) when a single edge is counted, and at least 2.5 system clocks when both edges are counted. Shorter pulses will not be counted correctly. Figure 9.5 shows the timing when both the rising and falling edges of the external clock are selected. |
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