HD6433644R datasheet(249/549 Pages) RENESAS

249 / 549 page

Section 9 Timers

Rev. 6.00 Sep 12, 2006 page 229 of 526

REJ09B0326-0600

9.4.4

Timer V Operation Modes

Table 9.10 summarizes the timer V operation states.

Table 9.10 Timer V Operation States

Operation Mode

Reset

Active

Sleep

Watch

Sub-

active

Sub-

sleep

Standby

TCNTV

Reset

Functions

Reset

TCRV0, TCRV1

Reset

Functions

Reset

TCORA, TCORB

Reset

Functions

Reset

TCSRV

Reset

Functions

Reset

9.4.5

Interrupt Sources

Timer V has three interrupt sources: CMIA, CMIB, and OVI. Table 9.11 lists the interrupt sources

and their vector address. Each interrupt source can be enabled or disabled by an interrupt enable

bit in TCRV0. Although all three interrupts share the same vector, they have individual interrupt

flags, so software can discriminate the interrupt source.

Table 9.11 Timer V Interrupt Sources

Interrupt

Description

Vector Address

CMIA

Generated from CMFA

H'0022

CMIB

Generated from CMFB

OVI

Generated from OVF

9.4.6

Application Examples

Pulse Output with Arbitrary Duty Cycle: Figure 9.11 shows an example of output of pulses

with an arbitrary duty cycle. To set up this output:

• Clear bit CCLR1 to 0 and set bit CCLR0 to 1 in TCRV0 so that TCNTV will be cleared by

compare match with TCORA.

• Set bits OS3 to OS0 to 0110 in TCSRV so that the output will go to 1 at compare match with

TCORA and to 0 at compare match with TCORB.

• Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source.

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