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HD6433644R Datasheet(PDF) 253 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 253 Page - Renesas Technology Corp |
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253 / 549 page ![]() Section 9 Timers Rev. 6.00 Sep 12, 2006 page 233 of 526 REJ09B0326-0600 Contention between TCNTV Write and Increment: If a TCNTV increment clock signal is generated in the T3 state of a TCNTV write cycle, the write takes precedence and the counter is not incremented. Figure 9.14 shows the timing. T1 T2 T3 TCNTV write cycle by CPU Address Internal write signal φ TCNTV clock TCNTV N M TCNTV write data TCNTV address Figure 9.14 Contention between TCNTV Write and Increment |
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