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HD6433644R Datasheet(PDF) 254 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 254 Page - Renesas Technology Corp |
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254 / 549 page ![]() Section 9 Timers Rev. 6.00 Sep 12, 2006 page 234 of 526 REJ09B0326-0600 Contention between TCOR Write and Compare Match: If a compare match is generated in the T3 state of a TCORA or TCORB write cycle, the write to TCORA or TCORB takes precedence and the compare match signal is inhibited. Figure 9.15 shows the timing. T1 T2 T3 TCORA write cycle by CPU Address Internal write signal φ TCNTV TCORA N M TCORA write data TCORA address N N + 1 Compare match signal Inhibited Figure 9.15 Contention between TCORA Write and Compare Match |
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