HD6433644R datasheet(243/549 Pages) RENESAS

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Section 9 Timers

Rev. 6.00 Sep 12, 2006 page 223 of 526

REJ09B0326-0600

Timer Control Register V1 (TCRV1)

Bit



TVEG1

TVEG0

TRGE



ICKS0

Initial value

Read/Write



R/W



R/W

TCRV1 is an 8-bit read/write register that selects the valid edge at the TRGV pin, enables TRGV

input, and selects the clock input to TCNTV.

TCRV1 is initialized to H'E2 upon reset and in watch mode, subsleep mode, and subactive mode.

Bits 7 to 5



Reserved Bits: Bit 7 to 5 are reserved; they are always read as 1, and cannot be

modified.

Bits 4 and 3



TRGV Input Edge Select (TVEG1, TVEG0): Bits 4 and 3 select the TRGV input

edge.

Bit 4: TVEG1

Bit 3: TVEG0

Description

TRGV trigger input is disabled

(initial value)

Rising edge is selected

Falling edge is selected

Rising and falling edges are both selected

Bit 2



TRGV Input Enable (TRGE): Bit 2 enables TCNTV counting to be triggered by input at

the TRGV pin, and enables TCNTV counting to be halted when TCNTV is cleared by compare

match. TCNTV stops counting when TRGE is set to 1, then starts counting when the edge selected

by bits TVEG1 and TVEG0 is input at the TRGV pin.

Bit 2: TRGE

Description

TCNTV counting is not triggered by input at the TRGV pin, and does not stop

when TCNTV is cleared by compare match

(initial value)

TCNTV counting is triggered by input at the TRGV pin, and stops when TCNTV

is cleared by compare match

Bit 1



Reserved Bit: Bit 1 is reserved; it is always read as 1, and cannot be modified.

Bit 0



Internal Clock Select 0 (ICKS0): Bit 0 and bits CKS2 to CKS0 in TCRV0 select the

TCNTV clock source. For details see section 9.4.2, Register Descriptions.

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