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HD6433644R Datasheet(PDF) 239 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 239 Page - Renesas Technology Corp |
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239 / 549 page  Section 9 Timers Rev. 6.00 Sep 12, 2006 page 219 of 526 REJ09B0326-0600 Timer Control Register V0 (TCRV0) Bit 7 6 5 4 3 2 1 0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCRV0 is an 8-bit read/write register that selects the TCNTV input clock, controls the clearing of TCNTV, and enables interrupts. TCRV0 is initialized to H'00 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. Bit 7 Compare Match Interrupt Enable B (CMIEB): Bit 7 enables or disables the interrupt request (CMIB) generated from CMFB when CMFB is set to 1 in TCSRV. Bit 7: CMIEB Description 0 Interrupt request (CMIB) from CMFB disabled (initial value) 1 Interrupt request (CMIB) from CMFB enabled Bit 6 Compare Match Interrupt Enable A (CMIEA): Bit 6 enables or disables the interrupt request (CMIA) generated from CMFA when CMFA is set to 1 in TCSRV. Bit 6: CMIEA Description 0 Interrupt request (CMIA) from CMFA disabled (initial value) 1 Interrupt request (CMIA) from CMFA enabled Bit 5 Timer Overflow Interrupt Enable (OVIE): Bit 5 enables or disables the interrupt request (OVI) generated from OVF when OVF is set to 1 in TCSRV. Bit 5: OVIE Description 0 Interrupt request (OVI) from OVF disabled (initial value) 1 Interrupt request (OVI) from OVF enabled Bits 4 and 3 Counter Clear 1 and 0 (CCLR1, CCLR0): Bits 4 and 3 specify whether or not to clear TCNTV, and select compare match A or B or an external reset input. When clearing is specified, if TRGE is set to 1 in TCRV1, then when TCNTV is cleared it is also halted. Counting resumes when a trigger edge is input at the TRGV pin. |
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