SH7785 datasheet(142/1692 Pages) RENESAS

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5. Exception Handling

Rev.1.00 Jan. 10, 2008 Page 112 of 1658

REJ09B0261-0100

(7)

Instruction Address Error

• Sources:

⎯ Instruction fetch from other than a word boundary (2n +1)

⎯ Instruction fetch from area H'80000000 to H'FFFFFFFF in user mode

Area H'E5000000 to H'E5FFFFFF can be accessed in user mode. For details, see section 9,

On-Chip Memory.

• Transition address: VBR + H'00000100

• Transition operations:

The virtual address (32 bits) at which this exception occurred is set in TEA, and the

corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates

the ASID when this exception occurred.

The PC and SR contents for the instruction at which this exception occurred are saved in the

SPC and SSR. The R15 contents at this time are saved in SGR.

Exception code H'0E0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a

branch is made to PC = VBR + H'0100. For details, see section 7, Memory Management Unit

(MMU).

Instruction_address_error()

{

TEA = EXCEPTION_ADDRESS;

PTEH.VPN = PAGE_NUMBER;

SPC = PC;

SSR = SR;

SGR = R15;

EXPEVT = H'0000 00E0;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

PC = VBR + H'0000 0100;

}

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