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SH7785 Datasheet(PDF) 144 Page - Renesas Technology Corp

Part # SH7785
Description  32-Bit RISC Microcomputer
PDF  1692 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7785 Datasheet(HTML) 144 Page - Renesas Technology Corp

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5. Exception Handling
Rev.1.00 Jan. 10, 2008 Page 114 of 1658
REJ09B0261-0100
(9)
General Illegal Instruction Exception
• Sources:
⎯ Decoding of an undefined instruction not in a delay slot
Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
Undefined instruction: H'FFFD
⎯ Decoding in user mode of a privileged instruction not in a delay slot
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC
instructions that access GBR
• Transition address: VBR + H'00000100
• Transition operations:
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR. The R15 contents at this time are saved in SGR.
Exception code H'180 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0100. Operation is not guaranteed if an undefined code other
than H'FFFD is decoded.
General_illegal_instruction_exception()
{
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = H'0000 0180;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'0000 0100;
}



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