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SH7785 Datasheet(PDF) 153 Page - Renesas Technology Corp |
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SH7785 Datasheet(HTML) 153 Page - Renesas Technology Corp |
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153 / 1692 page ![]() 5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 123 of 1658 REJ09B0261-0100 5.7 Usage Notes (1) Return from Exception Handling A. Check the BL bit in SR with software. If SPC and SSR have been saved to memory, set the BL bit in SR to 1 before restoring them. B. Issue an RTE instruction. When RTE is executed, the SPC contents are saved in PC, the SSR contents are saved in SR, and branch is made to the SPC address to return from the exception handling routine. (2) If a General Exception or Interrupt Occurs When BL Bit in SR = 1 A. General exception When a general exception other than a user break occurs, the PC value for the instruction at which the exception occurred in SPC, and a manual reset is executed. The value in EXPEVT at this time is H'00000020; the SSR contents are undefined. B. Interrupt If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after the BL bit in SR has been cleared to 0 by software. If a nonmaskable interrupt (NMI) occurs, it can be held pending or accepted according to the setting made by software. In sleep or standby mode, however, an interrupt is accepted even if the BL bit in SR is set to 1. (3) SPC when an Exception Occurs A. Re-execution type general exception The PC value for the instruction at which the exception occurred is set in SPC, and the instruction is re-executed after returning from the exception handling routine. If an exception occurs in a delay slot instruction, however, the PC value for the delayed branch instruction is saved in SPC regardless of whether or not the preceding delay slot instruction condition is satisfied. B. Completion type general exception or interrupt The PC value for the instruction following that at which the exception occurred is set in SPC. If an exception occurs in a branch instruction with delay slot, however, the PC value for the branch destination is saved in SPC. (4) RTE Instruction Delay Slot A. The instruction in the delay slot of the RTE instruction is executed only after the value saved in SSR has been restored to SR. The acceptance of the exception related to the instruction access is determined depending on SR before restoring, while the acceptance of |
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