SH7785 datasheet(151/1692 Pages) RENESAS

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5. Exception Handling

Rev.1.00 Jan. 10, 2008 Page 121 of 1658

REJ09B0261-0100

The code corresponding to the each interrupt source is set in INTEVT. The BL, MD, and RB

bits are set to 1 in SR, and a branch is made to VBR + H'0600. When the INTMU bit in

CPUOPM is 1, IMASK bit in SR is changed to accepted interrupt level. For details, see section

10, Interrupt Controller (INTC).

Module_interruption()

{

SPC = PC;

SSR = SR;

SGR = R15;

INTEVT = H'0000 0400 ~ H'0000 3FE0;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

if (cond) SR.IMASK = level_of accepted_interrupt ();

PC = VBR + H'0000 0600;

}

5.6.4

Priority Order with Multiple Exceptions

With some instructions, such as instructions that make two accesses to memory, and the

indivisible pair comprising a delayed branch instruction and delay slot instruction, multiple

exceptions occur. Care is required in these cases, as the exception priority order differs from the

normal order.

(1)

Instructions that Make Two Accesses to Memory

With MAC instructions, memory-to-memory arithmetic/logic instructions, TAS instructions, and

MOVUA instructions, two data transfers are performed by a single instruction, and an exception

will be detected for each of these data transfers. In these cases, therefore, the following order is

used to determine priority.

1. Data address error in first data transfer

2. TLB miss in first data transfer

3. TLB protection violation in first data transfer

4. Initial page write exception in first data transfer

5. Data address error in second data transfer

6. TLB miss in second data transfer

7. TLB protection violation in second data transfer

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