SH7021 datasheet(367/509 Pages) RENESAS

367 / 509 page

RENESAS 352

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Bit 6 (receive data register full (RDRF)): RDRF indicates that RDR contains received data.

Bit 6: RDRF

Description

RDR does not contain valid received data (initial value)

RDRF is cleared to 0 when:

• The chip is reset or enters standby mode

• Software reads RDRF after it has been set to 1, then writes 0 in RDRF

• The DMAC reads data from RDR

RDR contains valid received data.

RDRF is set to 1 when serial data is received normally and transferred from

RSR to RDR.

Note:

The RDR and RDRF are not affected by detection of receive errors or by clearing of the RE

bit to 0 in the serial control register. They retain their previous contents. If RDRF is still set

to 1 when reception of the next data ends, an overrun error (ORER) occurs and the

received data is lost.

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Bit 5 (overrun error (ORER)): Indicates that data reception ended abnormally due to an

overrun error.

Bit 5: ORER

Description

Receiving is in progress or has ended normally (initial value)*1

ORER is cleared to 0 when:

• The chip is reset or enters standby mode

• Software reads ORER after it has been set to 1, then writes 0 in ORER

A receive overrun error occurred*2

ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1

Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which

retains its previous value.

2. RDR continues to hold the data received before the overrun error, so subsequent

receive data is lost. Serial receiving cannot continue while ORER is set to 1. In the

clocked synchronous mode, serial transmitting is disabled.

SH7021 Datasheet(PDF) 367 Page - Renesas Technology Corp