SH7021 datasheet(365/509 Pages) RENESAS

365 / 509 page

RENESAS 350

•

Bit 2 (transmit-end interrupt enable (TEIE)): TEIE enables or disables the transmit-end

interrupt (TEI) requested if TDR does not contain new transmit data when the MSB is

transmitted.

Bit 2: TEIE

Description

Transmit-end interrupt (TEI) requests are disabled* (initial value)

The TEI request can be cleared by reading the TDRE bit in the serial

status register (SSR) after it has been set to 1, then clearing TDRE to

0; by clearing the transmit end (TEND) bit to 0; or by clearing the TEIE

bit to 0.

Transmit-end interrupt (TEI) requests are enabled.

•

Bits 1 and 0 (clock enable 1 and 0 (CKE1 and CKE0)): CKE1 and CKE0 select the SCI clock

source and enable or disable clock output from the SCK pin. Depending on the combination of

CKE1 and CKE0, the SCK pin can be used for general-purpose input/output, serial clock

output, or serial clock input.

The CKE0 setting is valid only in the asynchronous mode, and only when the SCI is internally

clocked (CKE1 = 0). The CKE0 setting is ignored in the clocked synchronous mode, or when

an external clock source is selected (CKE1 = 1). Select the SCI operating mode in the serial

mode register (SMR) before setting CKE1 and CKE0. For further details on selection of the

SCI clock source, see table 13.9 in section 13.3, Operation.

Bit 1:

CKE1

Bit 0:

CKE0

Description*1

Synchronous mode

Internal clock, SCK pin used for input pin (input

signal is ignored or output pin output level is

undefined)

Clocked synchronous mode

Internal clock, SCK pin used for serial clock output*2

Synchronous mode

Internal clock, SCK pin used for clock output*3

Clocked synchronous mode

Internal clock, SCK pin used for serial clock output

Synchronous mode

External clock, SCK pin used for clock input*4

Clocked synchronous mode

External clock, SCK pin used for serial clock input

Synchronous mode

External clock, SCK pin used for clock input*4

Clocked synchronous mode

External clock, SCK pin used for serial clock input

Notes: 1. The SCK pin is multiplexed with other functions. Set the pin function controller (PFC) to

select the SCK function and the SCK input/output of the SCK pin.

2. Initial value

3. The output clock frequency is the same as the bit rate.

4. The input clock frequency is 16 times the bit rate.

SH7021 Datasheet(PDF) 365 Page - Renesas Technology Corp

SH7021 Datasheet(HTML) 365 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL