SH7021 datasheet(138/509 Pages) RENESAS

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8.3.5

Area Description

Area 0: Area 0 is the area where addresses A26–A24 are 000 and its address range is H'0000000–

H'0FFFFFF and H'8000000–H'8FFFFFF. Figure 8.5 is a memory map of area 0.

Area 0 can be set for use as on-chip ROM space or external memory space with the mode pins

(MD2–MD0). The MD2–MD0 pins also determine the bus width, regardless of the A27 address

bit. When MD2–MD0 are 000, area 0 is an 8-bit external memory space; when they are 001, area

0 is a 16-bit external memory space; and when they are 010, it is a 32-bit on-chip ROM space.

In the SH7020, the capacity of the on-chip ROM is 16 kbyte, so bits A23–A14 are ignored in on-

chip ROM space and the shadow is in 16 kbyte units. In the SH7021, the capacity of the on-chip

ROM is 32 kbyte, so bits A23–A15 are ignored in on-chip ROM space and the shadow is in 32

kbyte units. The

CSO signal is disabled in on-chip ROM space.

In external memory space, the A23 and A22 bits are not output and the shadow is in 4-Mbyte

units. When external memory space is accessed, the

CS0 signal is valid. The external memory

space has a long wait function, so between 1 and 4 states can be selected for the number of long

waits inserted into the bus cycle using the areas 0 and 2 long wait insertion bits (A02LW1,

A02LW0) of wait state controller 3 (WCR3).

SH7021 Datasheet(PDF) 138 Page - Renesas Technology Corp