SH7021 datasheet(136/509 Pages) RENESAS

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Table 8.7

A26–A24 Bits and Chip Select Signals

Address

A26

A25

A24

Area Selected

Chip Select Pin Driven Low

Area 0

CS0

Area 1

CS1

Area 2

CS2

Area 3

CS3

Area 4

CS4

Area 5

CS5

Area 6

CS6

Area 7

CS7

The chip select signal is output only for external accesses. When accessing the on-chip ROM (area

0), on-chip peripheral modules (area 5) and on-chip RAM (area 7), the

CS0, CS5, and CS7 pins

are not driven low. When accessing DRAM space (area 1), select the

RAS and CAS signals with

the pin function controller.

8.3.4

Shadows

The size of each area is 16 Mbytes, which can be specified with 24 address bits A23–A0 for 8-bit

spaces and 16-bit spaces alike. Bits A23 and A22, however, output externally only when the

address multiplex function is used in DRAM space (area 1); in all other cases, there is no output,

so the actually accessible area for all areas is the 4 Mbyte that can be specified with 22 bits A21–

A0. No matter what the values of A23 and A22, the same 4 Mbytes of actual space is accessed. As

illustrated in figure 8.4 (a), the A23 and A22 bit regions 00, 01, 10 and 11 are called shadows of

actual areas. Shadows are allocated in 4-Mbyte units for both 8-bit and 16-bit bus widths. When

the same addresses H'3200000, H'3600000, H'3A00000 and H'3E00000 are specified for values

A21–A0, as shown in figure 8.4 (b), the same actual space is accessed regardless of the A23 and

A22 bits.

In areas whose bus widths are switchable using the A27 address bit, the shadow of the same actual

space is allocated to both A27 = 0 spaces and A27 = 1 spaces (figure 8.4(a)). When the value of

A27 is changed, the valid AD pins switch from AD15–AD0 to AD7–AD0, but the actual space

accessed remains the same.

The spaces of on-chip ROM (area 0), DRAM (area 1), on-chip peripheral modules (area 5) and on-

chip RAM (area 7) have shadows of different sizes from those discussed above. See section 8.3.5,

Description of Areas, for details.

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