SH7021 datasheet(134/509 Pages) RENESAS

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Table 8.6

How Space is Divided

Area Address

Assign-able Memory

Capacity

(linear space)

Bus

Width

Output

H'0000000 – H'0FFFFFF

On-chip ROM*1

16 kB*3

32 kB*4

—

External memory*2

4 MB

8/16*5

CS0

H'1000000 – H'1FFFFFF

External memory

4 MB

CS1

DRAM*6

16 MB

RAS CAS

H'2000000 – H'2FFFFFF

External memory

4 MB

CS2

H'3000000 – H'3FFFFFF

External memory

4 MB

CS3

H'4000000 – H'4FFFFFF

External memory

4 MB

CS4

H'5000000 – H'5FFFFFF

On-chip peripheral module

512 B

8/16*7

—

H'6000000 – H'6FFFFFF

External memory*9

4 MB

8/16*8

CS6

Multiplexed I/O

4 MB

H'7000000 – H'7FFFFFF

External memory

4 MB

CS7

H'8000000 – H'8FFFFFF

On-chip ROM*1

16 kB*3

32 kB*4

—

External memory*2

4 MB

8/16*5

CS0

H'9000000 – H'9FFFFFF

External memory

4 MB

CS1

DRAM*6

16 MB

RAS CAS

H'A000000 – H'AFFFFFF External memory

4 MB

CS2

H'B000000 – H'BFFFFFF External memory

4 MB

CS3

H'C000000 – H'CFFFFFF External memory

4 MB

CS4

H'D000000 – H'DFFFFFF External memory

4 MB

CS5

H'E000000 – H'EFFFFFF External memory

4 MB

CS6

H'F000000 – H'FFFFFFF On-chip RAM

1 kB

—

Notes: 1. When MD2–MD0 pins are 010

2. When MD2–MD0 pins are 000 or 001

3. For SH7020

4. For SH7021

5. Select with MD0 pin

6. Select with DRAME bit in BCR

7. Divided into 8-bit and 16-bit space according to value of address bit A8 (Long word

accesses are inhibited, however, in on-chip peripheral modules with bus widths of 8

bits. Some on-chip peripheral modules with bus widths of 16 bits also have registers

that are only byte-accessible and registers for which byte access is inhibited. For

details, see the sections on the individual modules.)

8. Divided into 8-bit space and 16-bit space by value of address bit A14

9. Select with IOE bit of BCR

SH7021 Datasheet(PDF) 134 Page - Renesas Technology Corp

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