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SH7021 Datasheet(PDF) 131 Page - Renesas Technology Corp |
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SH7021 Datasheet(HTML) 131 Page - Renesas Technology Corp |
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131 / 509 page ![]() RENESAS 113 Bit: 15 14 13 12 11 10 9 8 Bit name: PEF PFRC PEO PCHK1 PCHK0 — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W — — — Bit: 7 6 5 4 3 2 1 0 Bit name: — — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: — — — — — — — — • Bit 15 (parity error flag (PEF)): When a parity check is done, PEF indicates whether a parity error has occurred. 0 indicates that no parity error has occurred; 1 indicates that a parity error has occurred. Bit 15: PEF Description 0 No parity error (initial value). Cleared by reading PEF after it has been set to 1, then writing 0 in PEF. 1 Parity error has occurred. • Bit 14 (parity output force (PFRC)): PFRC selects whether to produce a forced parity output for testing the parity error check function. When cleared to 0, there is no forced output; when set to 1, it produces a forced output of high level from the DPH and DPL pins when data is output, regardless of the parity. Bit 14: PFRC Description 0 Parity output not forced (initial value) 1 High output forced • Bit 13 (parity polarity (PEO)): PEO selects even or odd parity. When cleared to 0, parity is even; when set to 1, parity is odd. Bit 13: PEO Description 0 Even parity (initial value) 1 Odd parity • Bits 12 and 11 (parity check enable bits 1, 0 (PCHK1 and PCHK0)): These bits determine whether or not a parity is checked and generated, and select the check and generation spaces. |
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