SH7021 datasheet(183/509 Pages) RENESAS

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BREQ is sampled one state before the bus cycle. If BREQ is input without satisfying tBRQS, the

bus is released after executing cycle B following the end of bus cycle A, as shown in figure 8.43.

The maximum number of states from

BREQ input to bus release are used when B is a cycle

comprising the maximum number of states for which the bus is not released; the number of states

is the maximum number of states for which bus is not released + approx. 4.5 states.

The maximum number of states for which the bus is not released requires careful investigation.

BREQ

Bus cycle

BACK

tBRQS

tBACD1

Bus release

Figure 8.43 When

BREQ is Input without Satisfying tBRQS

1. Cycles in which bus is not released

(a) One bus cycle

The bus is never released during one bus cycle. For example, in the case of a longword

read (or write) in 8-bit ordinary space, one bus cycle consists of 4 memory accesses to 8-bit

ordinary space, as shown in figure 8.44. The bus is not released between these accesses.

Assuming one memory access to require 2 states, the bus is not released for a period of 8

states.

8 bits 8 bits

Cycle during which

bus is not released

8 bits 8 bits

Figure 8.44 One Bus Cycle

(b) TAS instruction read cycle and write cycle

The bus is never released during a TAS instruction read cycle and write cycle (figure 8.45).

The TAS instruction read cycle and write cycle should be regarded as one bus cycle during

which the bus is not released.

SH7021 Datasheet(PDF) 183 Page - Renesas Technology Corp