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SH7021 Datasheet(PDF) 185 Page - Renesas Technology Corp |
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SH7021 Datasheet(HTML) 185 Page - Renesas Technology Corp |
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185 / 509 page ![]() RENESAS 167 2. Bus release procedure The bus release procedure is shown in figure 8.47. Figure 8.47 shows the case where BREQ is input one state before the break between bus cycles so that tBRQS is satisfied. In the SH7020 and SH7021, the bus is released after the bus cycle in which BREQ is input (if BREQ is input between bus cycles, after the bus cycle starting next). CK A21 to A0 BREQ BACK RD, WR RAS, CAS CSn tBRQS tBRQS tBZD tBZD tBACD1 tBACD1 Bus cycle Bus cycle Bus release Strobe pin: high-level output The bus is released after the bus cycle in which BREQ is input (if BREQ is input between bus cycles, after the bus cycle starting next). Bus cycle restart Address & data strobe pins: high impedance Figure 8.47 Bus Release Procedure |
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