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SH7021 Datasheet(PDF) 187 Page - Renesas Technology Corp |
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SH7021 Datasheet(HTML) 187 Page - Renesas Technology Corp |
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187 / 509 page  170 RENESAS Two on-chip peripheral modules (excluding DMAC) • Transfer requests External request (From DREQ pins (channels 0 and 1 only). DREQ can be detected either by edge or by level) Requests from on-chip peripheral modules (serial communications interface (SCI), and 16- bit integrated-timer pulse unit (ITU)) Auto-request (the transfer request is generated automatically within the DMAC) • Selectable bus modes: Cycle-steal mode or burst mode • Selectable channel priority levels: Fixed, round-robin, or external-pin round-robin modes • CPU can be asked for interrupt when data transfer ends • Maximum transfer rate 20 M words/s (320 MB/s) For 5V and 20 MHz Bus mode: Burst mode Transmit size: Word 9.1.2 Block Diagram Figure 9.1 is a block diagram of the DMAC. |
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