SH7021 datasheet(190/509 Pages) RENESAS

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9.1.4

Table 9.2 summarizes the DMAC registers. DMAC has a total of 17 registers. Each channel has

four control registers. One other control register is shared by all channels

Table 9.2

DMAC Registers

Chan-

nel

Name

Abbre-

viation

R/W

Initial

Value

Address

Access

Size

DMA source address register 0

SAR0*3

R/W

Undefined H'5FFFF40

16, 32

DMA destination address

DAR0*3

R/W

Undefined H'5FFFF44

16, 32

DMA transfer count register 0

TCR0*3

R/W

Undefined H'5FFFF4A

16, 32

DMA channel control register 0

CHCR0

R/(W)*1 H'0000

H'5FFFF4E

8, 16, 32

DMA source address register 1

SAR1*3

R/W

Undefined H'5FFFF50

16, 32

DMA destination address

DAR1*3

R/W

Undefined H'5FFFF54

16, 32

DMA transfer count register 1

TCR1*3

R/W

Undefined H'5FFFF5A

16, 32

DMA channel control register 1

CHCR1

R/(W)*1 H'0000

H'5FFFF5E

8, 16, 32

DMA source address register 2

SAR2*3

R/W

Undefined H'5FFFF60

16, 32

DMA destination address

DAR2*3

R/W

Undefined H'5FFFF64

16, 32

DMA transfer count register 2

TCR2*3

R/W

Undefined H'5FFFF6A

16, 32

DMA channel control register 2

CHCR2

R/(W)*1 H'0000

H'5FFFF6E

8, 16, 32

DMA source address register 3

SAR3*3

R/W

Undefined H'5FFFF70

16, 32

DMA destination address

DAR3*3

R/W

Undefined H'5FFFF74

16, 32

DMA transfer count register 3

TCR3*3

R/W

Undefined H'5FFFF7A

16, 32

DMA channel control register 3

CHCR3

R/(W)*1 H'0000

H'5FFFF7E

8, 16, 32

Shared

DMA operation register

DMAOR R/(W)*2 H'0000

H'5FFFF48

8, 16, 32

Notes: 1. Write 0 alone in bit 1 of CHCR0–CHCR3 to clear flags.

2. Write 0 alone in bits 1 and 2 of the DMAOR to clear flags.

3. Access SAR0–SAR3, DAR0–DAR3, and TCR0–TCR3 by long word or word. If byte

access is used when writing, the value of the register contents becomes undefined; if

used when reading, the value read is undefined.

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