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SH7021 Datasheet(PDF) 194 Page - Renesas Technology Corp |
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SH7021 Datasheet(HTML) 194 Page - Renesas Technology Corp |
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194 / 509 page ![]() RENESAS 177 Bit 11: RS3 Bit 10: RS2 Bit 9: RS1 Bit 8: RS0 Description 00 0 0 DREQ (External request*1, dual address mode) (initial value) 0 0 0 1 Reserved (illegal setting) 00 1 0 DREQ (External request*1, single address mode*2) 00 1 1 DREQ (External request*1, single address mode*3) 0 1 0 0 RXI0 (On-chip serial communication interface 0 receive data full interrupt transfer request)*4 0 1 0 1 TXI0 (On-chip serial communication interface 0 transmit data empty interrupt transfer request)*4 0 1 1 0 RXI1 (On-chip serial communication interface 1 receive data full interrupt transfer request)*4 0 1 1 1 TXI1 (On-chip serial communication interface 1 transmit data empty interrupt transfer request)*4 1 0 0 0 IMIA0 (On-chip ITU0 input capture/compare-match A interrupt transfer request)*4 1 0 0 1 IMIA1 (On-chip ITU1 input capture/compare-match A interrupt transfer request)*4 1 0 1 0 IMIA2 (On-chip ITU2 input capture/compare-match A interrupt transfer request)*4 1 0 1 1 IMIA3 (On-chip ITU3 input capture/compare-match A interrupt transfer request)*4 1 1 0 0 Auto-request (Transfer requests automatically generated within DMAC)*4 1 1 0 1 Reserved (illegal setting) 1 1 1 0 Reserved (illegal setting) 1 1 1 1 Reserved (illegal setting) SCI0, SCI1: Serial communications interface channels 0 and 1. ITU0–ITU3: Channels 0–3 of the 16-bit integrated-timer pulse unit. Notes: 1. These bits are valid only in channels 0 and 1. None of these request sources can be selected in channels 2 and 3. 2. Transfer from memory-mapped external device or external memory to external device with DACK. 3. Transfer from external device with DACK to memory-mapped external device or external memory. 4. Dual address mode. |
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