SH7021 datasheet(196/509 Pages) RENESAS

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Bit 3 (transfer size bit (TS)): TS selects the transfer unit size. If the on-chip peripheral module

that is the source or destination of the transfer can only be accessed in bytes, byte must be

selected in this bit. The TS bit is initialized to 0 by resets or in standby mode.

Bit 3: TS

Description

Byte (8 bits) (initial value)

Word (16 bits)

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Bit 2 (interrupt enable bit (IE)): IE determines whether or not to request a CPU interrupt at the

end of a DMA transfer. When the IE bit is set to 1, an interrupt (DEI) is requested from the

CPU when the TE bit is set. The IE bit is initialized to 0 by resets or in standby mode.

Bit 2: IE

Description

Interrupt request disabled (initial value)

Interrupt requeste enabled

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Bit 1 (transfer end flag bit (TE)): TE indicates that the transfer has ended. When a DMA

transfer ends normally and the value in the DMA transfer count register (TCR) becomes 0, the

TE bit is set to 1. This flag is not set if the transfer ends because of an NMI interrupt or address

error, or because the DE bit or the DME bit of the DMA operation register (DMAOR) was

cleared. To clear the TE bit, read 1 from it and then write 0.

When this flag is set, setting the DE bit to 1 does not enable a DMA transfer. The TE bit is

initialized to 0 by resets or in standby mode.

Bit 1: TE

Description

DMA has not ended or was aborted (initial value)

To clear TE, the CPU must read TE after it has been set to 1, then

write a 0 in this bit

DMA has ended normally

SH7021 Datasheet(PDF) 196 Page - Renesas Technology Corp