SH7021 datasheet(197/509 Pages) RENESAS

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180 RENESAS

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Bit 0 (DMA enable bit (DE)): DE enables or disables DMA transfers. In the auto-request

mode, the transfer starts when this bit or the DME bit of the DMAOR is set to 1. The TE bit

and the NMIF and AE bits of the DMAOR must be all cleared to 0. In external request mode

or on-chip peripheral module request mode, the transfer begins when the DMA transfer request

is received from said device or on-chip peripheral module, provided this bit and the DME bit

are set to 1. As with the auto request mode, the TE bit and the NMIF and AE bits of the

DMAOR must be all cleared to 0. The transfer can be stopped by clearing this bit to 0.

The DE bit is initialized to 0 by resets or in standby mode.

Bit 0: DE

Description

DMA transfer disabled (initial value)

DMA transfer enabled

9.2.5

DMA Operation Register (DMAOR)

The DMA operation register (DMAOR) is a 16-bit read/write register that controls the DMA

transfer mode. It also indicates the DMA transfer status. It is initialized to H'0000 by a reset or the

standby mode.

Bit:

Bit name:

——

—

PR1

PR0

Initial value:

R/W:

R/W

Bit:

Bit name:

—

NMIF

DME

Initial value:

R/W:

R/(W)*

Note:

Write only 0 to clear the flag.

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Bits 15–10 (reserved): These bits always read 0. The write value should always be 0.

SH7021 Datasheet(PDF) 197 Page - Renesas Technology Corp