SH7021 datasheet(193/509 Pages) RENESAS

193 / 509 page

176 RENESAS

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Bits 15 and 14 (destination address mode bits 1, 0 (DM1 and DM0)): DM1 and DM0 select

whether the DMA destination address is incremented, decremented, or left fixed (in the single

address mode, DM1 and DM0 are ignored when transfers are made from memory-mapped

external devices or external memory to external devices with DACK). DM1 and DM0 are

initialized to 00 by resets or in standby mode.

Bit 15: DM1

Bit 14: DM0

Description

Fixed destination address (initial value)

Destination address is incremented (+1 or +2 depending on if

the transfer size is word or byte)

Destination address is decremented (–1 or –2 depending on if

the transfer size is word or byte)

Reserved (illegal setting)

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Bits 13 and 12 (source address mode bits 1, 0 (SM1 and SM0)): SM1 and SM0 select whether

the DMA source address is incremented, decremented, or left fixed (in the single address

mode, SM1 and SM0 are ignored when transfers are made from external devices with DACK

to memory-mapped external devices or external memory). SM1 and SM0 are initialized to 00

by resets or in standby mode.

Bit 13: SM1

Bit 12: SM0

Description

Fixed source address (initial value)

Source address is incremented (+1 or +2 depending on if the

transfer size is word or byte)

Source address is decremented (–1 or –2 depending on if the

transfer size is word or byte)

Reserved (illegal setting)

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Bits 11–8 (resource select bits 3–0 (RS3-RS0)): RS3–RS0 specify which transfer requests will

be sent to the DMAC. Do not change the transfer request source unless the DMA enable bit

(DE) is 0. The RS3–RS0 bits are initialized to 0000 by resets or in standby mode.

SH7021 Datasheet(PDF) 193 Page - Renesas Technology Corp