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SH7021 Datasheet(PDF) 188 Page - Renesas Technology Corp |
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SH7021 Datasheet(HTML) 188 Page - Renesas Technology Corp |
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188 / 509 page  RENESAS 171 DREQ0 , DREQ1 ITU SCI DACK0, DACK1 DEIn DMAC On-chip ROM On-chip RAM On-chip peripheral module External ROM External RAM External device (memory mapped) External device (with acknowledge) Bus controller Iteration control Register control Start-up control Request priority control Bus interface SARn DARn TCRn CHCRn DMAOR DMAOR: DMA operation register SARn: DMA source address register DARn: DMA destination address register TCRn: DMA transfer count register CHCRn: DMA channel control register DEIn: DMA transfer-end interrupt request to CPU. n: 0–3 Figure 9.1 DMAC Block Diagram |
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