SH7021 datasheet(238/509 Pages) RENESAS

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10.1.4

Table 10.3 summarizes the ITU register configuration.

Table 10.3

Channel Name

Abbrevi-

ation

R/W

Initial

Value

Address*1

Access

Size

Shared

Timer start register

TSTR

R/W

H'E0/H'60 H'5FFFF00

Timer synchro register

TSNC

R/W

H'E0/H'60 H'5FFFF01

Timer mode register

TMDR

R/W

H'80/H'00

H'5FFFF02

Timer function control register TFCR

R/W

H'C0/H'40 H'5FFFF03

Timer output control register

TOCR

R/W

H'FF/H'7F H'5FFFF31

Timer control register 0

TCR0

R/W

H'80/H'00

H'5FFFF04

Timer I/O control register 0

TIOR0

R/W

H'88/H'08

H'5FFFF05

Timer interrupt enable

TIER0

R/W

H'F8/H'78

H'5FFFF06

Timer status register 0

TSR0

R/(W)*2

H'F8/H'78

H'5FFFF07

Timer counter 0

TCNT0

R/W

H'00

H'5FFFF08

8, 16, 32

H'5FFFF09

8, 16, 32

General register A0

GRA0

R/W

H'FF

H'5FFFF0A

8, 16, 32

H'5FFFF0B

8, 16, 32

General register B0

GRB0

R/W

H'FF

H'5FFFF0C 8, 16

H'5FFFF0D 8, 16

Timer control register 1

TCR1

R/W

H'80/H'00

H'5FFFF0E

Timer I/O control register 1

TIOR1

R/W

H'88/H'08

H'5FFFF0F

Timer interrupt enable

TIER1

R/W

H'F8/H'78

H'5FFFF10

Timer status register 1

TSR1

R/(W)*2

H'F8/H'78

H'5FFFF11

Timer counter 1

TCNT1

R/W

H'00

H'5FFFF12

8, 16

H'5FFFF13

8, 16

General register A1

GRA1

R/W

H'FF

H'5FFFF14

8, 16, 32

H'5FFFF15

8, 16, 32

General register B1

GRB1

R/W

H'FF

H'5FFFF16

8, 16, 32

H'5FFFF17

8, 16, 32

SH7021 Datasheet(PDF) 238 Page - Renesas Technology Corp

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