SH7021 datasheet(263/509 Pages) RENESAS

263 / 509 page

RENESAS 247

•

Free-running count and periodic count

A reset of the counters for channels 0–4 leaves them all in the free-running mode. When a

corresponding bit in the TSTR is set to 1, the corresponding timer counter operates as a free-

running counter and begins to increment. When the count wraps around from H'FFFF–H'0000,

the overflow flag (OVF) in the timer status register (TSR) is set to 1. If the OVIE bit in the

timer’s corresponding interrupt enable register (TIER) is set to 1, the CPU will be asked for an

interrupt. After the TCNT overflows, counting continues from H'0000. Figure 10.15 shows an

example of free-running counting.

Periodic counter operation is obtained for a given channel’s TCNT by selecting compare match

as a TCNT clear source. (Set the GRA or GRB for period setting to output compare register

and select counter clear upon compare match using the CCLR1 and CCLR0 bits of the timer

control register (TCR).) After setting, the TCNT begins incrementing as a periodic counter

when the corresponding bit of TSTR is set to 1. When the count matches GRA or GRB, the

IMFA/IMFB bit in the TSR is set to 1 and the counter is automatically cleared to H'0000. If the

IMIEA/IMIEB bit of the corresponding TIER is set to 1 at this point, the CPU will be asked for

an interrupt. After the compare match, TCNT continues counting from H'0000. Figure 10.16

shows an example of periodic counting.

H'FFFF

H'0000

STR0–STR4

OVF

TCNT value

Time

Figure 10.15 Free-Running Counter Operation

SH7021 Datasheet(PDF) 263 Page - Renesas Technology Corp