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SH7021 Datasheet(PDF) 259 Page - Renesas Technology Corp |
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SH7021 Datasheet(HTML) 259 Page - Renesas Technology Corp |
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259 / 509 page ![]() RENESAS 243 TCNTH TCNTL H L Bus interface H L CPU Internal data bus Module data bus Figure 10.9 Accessing TCNT (CPU–TCNT (lower byte)) TCNTH TCNTL H L Bus interface H L CPU Internal data bus Module data bus Figure 10.10 Accessing TCNT (TCNT–CPU (upper byte)) TCNTH TCNTL H L Bus interface H L CPU Internal data bus Module data bus Figure 10.11 Accessing TCNT (TCNT–CPU (lower byte)) 10.3.2 8-Bit Accessible Registers All registers other than the TCNT, general registers, and buffer registers are 8-bit registers. These are connected to the CPU by an 8-bit data bus. Figures 10.12 and 10.13 illustrate reading and writing in byte units with the timer control register (TCR). These registers must be accessed by byte access. |
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