SH7021 datasheet(257/509 Pages) RENESAS

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Bit:

Bit name:

——

—

OVIE

IMIEB

IMIEA

Initial value:

R/W:

——

—

R/W

Note:

Undefined

•

Bits 7–3 (reserved): Bit 7 is read as undefined. Bits 6–3 are always read as 1. The write value

to bit 7 should be 0 or 1. The write value to bits 6–3 should always be 1.

•

Bit 2 (overflow interrupt enable (OVIE)): When the TSR overflow flag (OVF) is set to 1,

OVIE enables or disables interrupt requests from the OVF.

Bit 2: OVIE

Description

Disables interrupt requests by the OVF (initial value)

Enables interrupt requests from the OVF

•

Bit 1 (input capture/compare match interrupt enable B (IMIEB)): When the IMFB bit of the

TSR is set to 1, IMIEB enables or disables the interrupt requests from the IMFB.

Bit 1: IMIEB

Description

Disables interrupt requests by the IMFB (IMIB) (initial value)

Enables interrupt requests from the IMFB (IMIB)

•

Bit 0 (input capture/compare match interrupt enable A (IMIEA)): When the IMFA bit of the

TSR is set to 1, IMIEA enables or disables the interrupt requests from the IMFA.

Bit 0: IMIEA

Description

Disables interrupt requests by the IMFA (IMIA) (initial value)

Enables interrupt requests from the IMFA (IMIA)

10.3

CPU Interface

10.3.1

16-Bit Accessible Registers

The timer counters (TCNT), general registers A and B (GRA, GRB), and buffer registers A and B

(BRA, BRB) are 16-bit registers. The SH CPU can access these registers a word at a time using a

16-bit data bus. Byte access is also possible. Read and write operations performed on the TCNT in

word units are shown in figures 10.6 and 10.7. Byte-unit read and write operations on TCNTH and

TCNTL are shown in figures 10.8–10.11.

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