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Bit 1 (input capture/compare match B (IMFB)): IMFB indicates a GRB compare match or

input capture.

Bit 1: IMFB

Description

Clearing condition: Read IMFB when IMFB = 1, then write 0 in IMFB

(initial value)

Setting condition:

• GRB is functioning as an output compare register and TCNT = GRB

• GRB is functioning as an input capture register and the value of

TCNT is transferred to GRB by an input capture signal

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Bit 0 (input capture/compare match A (IMFA)): IMFA indicates a GRA compare match or

input capture.

Bit 0: IMFA

Description

Read IMFA when IMFA = 1, then write 0 in IMFA (initial value).

Clearing condition: DMAC is activated by an IMIA interrupt (only

channels 0–3)

Setting condition:

• GRA is functions as an output compare register and TCNT = GRA

• GRA is functioning as an input capture register and the value of

TCNT is transferred to GRA by an input capture signal

10.2.12

Timer Interrupt Enable Register (TIER)

The timer status interrupt enable register (TIER) is an eight-bit read/write register that controls

enabling/disabling of overflow interrupt requests and general register compare match/input capture

interrupt requests. TIER is initialized by a reset or standby mode to H'F8 or H'78. Each ITU

channel has one TIER (table 10.10).

Table 10.10 Timer Interrupt Enable Register (TIER)

Channel

Abbreviation

Function

TIER0

The TIER controls interrupt enable/disable.

TIER1

TIER2

TIER3

TIER4

SH7021 Datasheet(PDF) 256 Page - Renesas Technology Corp