SH7021 datasheet(253/509 Pages) RENESAS

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Bit 2:

TPSC2

Bit 1:

TPSC1

Bit 0:

TPSC0 Counter Clock (and cycle when

φ = 10 MHz)

Internal clock

φ (initial value)

Internal clock

φ/2

Internal clock

φ/4

Internal clock

φ/8

External clock A (TCLKA)

External clock B (TCLKB)

External clock C (TCLKC)

External clock D (TCLKD)

10.2.10

Timer I/O Control Register (TIOR)

The timer I/O control register (TIOR) is an eight-bit read/write register that selects the output

compare or input capture function for the general registers GRA and GRB. It also selects the

function of the TIOCA and TIOCB pins. If output compare is selected, the TIOR also selects the

output settings. If input capture is selected, the TIOR also select the input capture edges. TIOR is

initialized to H'88 or H'08 on a reset or standby mode. Each ITU channel has one TIOR (table

10.8).

Table 10.8

Timer I/O Control Register (TIOR)

Channel

Abbre-

viation

Function

TIOR0

The TIOR controls the GRs. Some functions vary during PWM. When

TIOR1

channels 3 and 4 are set for complementary PWM mode/reset-synchronized

TIOR2

PWM mode, TIOR3 and TIOR4 settings are not valid.

TIOR3

TIOR4

Bit:

Bit name:

—

IOB2

IOB1

IOB0

—

IOA2

IOA1

IOA0

Initial value:

R/W:

—

R/W

—

R/W

Note:

Undefined

•

Bit 7 (reserved): Bit 7 is read as undefined. The write value should be 0 or 1.

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