SH7021 datasheet(250/509 Pages) RENESAS

250 / 509 page

234 RENESAS

General registers are connected to the CPU by a 16-bit bus, so general registers can be written or

read by either word access or byte access. General registers are initialized to the output compare

Table 10.5

General Registers A and B (GRA and GRB)

Channel

Abbreviation

Function

GRA0, GRB0

Output compare/input capture dual register

GRA1, GRB1

GRA2, GRB2

GRA3, GRB3

Output compare/input capture dual register. Can also be set for

GRA4, GRB4

buffer operation in combination with the buffer registers (BRA, BRB)

Bit:

Bit name:

Initial value:

R/W:

R/W

Bit:

Bit name:

Initial value:

R/W:

R/W

10.2.8

Buffer Registers A and B (BRA, BRB)

Each buffer register is a 16-bit read/write register that is used in the buffer mode. The ITU has

four buffer registers, two each for channels 3 and 4 (table 10.6). Buffer operation can be set

independently by the timer function control register (TFCR) bits BFB4, BFA4, BFB3, and BFB3

bits. The buffer registers are paired with the general registers and their function changes

automatically to match the function of its corresponding general register.

The buffer registers are connected to the CPU by a 16-bit bus, so they can be written or read by

either word or byte access. Buffer registers are initialized to H'FFFF by a reset or in standby mode.

SH7021 Datasheet(PDF) 250 Page - Renesas Technology Corp