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PWM Mode: In PWM mode, a PWM waveform is output from the TIOCA pin. Output becomes

1 upon compare match A and 0 upon compare match B. GRA and GRB can be set so that the

PWM waveform output has a duty cycle between 0% and 100%. When set for PWM mode, the

GRA and GRB automatically become output compare registers.

Reset-synchronized PWM Mode: Three pairs of positive and negative PWM waveforms can be

obtained using channels 3 and 4 (the three phases of the PWM waveform share a transition point

on one side). When set for reset-synchronized PWM mode, GRA3, GRB3, GRA4, and GRB4

automatically become output compare registers. The TIOCA3, TIOCB3, TIOCA4, TOCXA4,

TIOCB4, and TOCXB4 pins also automatically become PWM output pins and TCNT3 becomes

an upcounter. TCNT4 functions independently (although GRA and GRB are isolated from

TCNT4).

Complementary PWM Mode: Three pairs of complementary positive and negative PWM

waveforms whose positive and negative phases do not overlap can be obtained using channels 3

and 4. When set for complementary PWM mode, GRA3, GRB3, GRA4, and GRB4 automatically

become output compare registers. The TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and

TOCXB4 pins also automatically become PWM output pins while TCNT3 and TCNT4 become

upcounters.

Phase Counting Mode: In phase counting mode, the phase differential between two clocks input

from the TCLKA and TCLKB pins is detected and the TCNT2 operates as an up/downcounter. In

phase counting mode, the TCLKA and TCLKB pins become clock inputs and TCNT2 functions as

an up/downcounter.

Buffer Mode:

•

When GR is an output compare register: The BR value of each channel is transferred to the GR

when a compare match occurs.

•

When GR is an input capture register: The TCNT value is transferred to the GR when an input

capture occurs and simultaneously the value previously stored in the GR is transferred to the

BR.

•

Complementary PWM mode: When the TCNT3 and TCNT4 change count directions, the BR

value is transferred to the GR.

•

Reset-synchronized PWM mode: The BR value is transferred to GR upon a GRA3 compare

match.

10.4.2

Basic Functions

Counter Operation: When a start bit (STR0–STR4) in the timer start register (TSTR) is set to 1,

the corresponding timer counter (TCNT) starts counting. There are two counting modes: a free-

running mode and a periodic mode.

SH7021 Datasheet(PDF) 261 Page - Renesas Technology Corp