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10.5.3

Interrupt Sources and Activating the DMAC

The ITU has compare match/input capture A interrupts, compare match/input capture B interrupts

and overflow interrupts for each channel. Each of the fifteen of these three types of interrupts are

allocated their own independently vectored addresses. When the interrupt’s interrupt request flag

is set to 1 and the interrupt enable bit is set to 1, the interrupt is requested.

The channel priority order can be changed with the interrupt controller. For more information, see

section 5, Interrupt Controller. The compare match/input capture A interrupts of channels 0–3 can

start the DMAC to transfer data. Table 10.17 lists the interrupt sources.

Table 10.17 ITU Interrupt Sources

Channel

Interrupt

Source

Description

DMAC

Activation

Priority

Order*

IMIA0

Compare match or input capture A0

Yes

High

IMIB0

Compare match or input capture B0

↑

OVI0

Overflow 0

IMIA1

Compare match or input capture A1

Yes

IMIB1

Compare match or input capture B1

OVI1

Overflow 1

IMIA2

Compare match or input capture A2

Yes

IMIB2

Compare match or input capture B2

OVI2

Overflow 2

IMIA3

Compare match or input capture A3

Yes

IMIB3

Compare match or input capture B3

OVI3

Overflow 3

IMIA4

Compare match or input capture A4

IMIB4

Compare match or input capture B4

↓

OVI4

Overflow 4

Low

Note:

Indicates the initial status following reset. The ranking of channels can be altered using the

interrupt controller.

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